1. Field of the Invention
The present invention relates generally to semiconductor devices and more particularly to lightly opened drain MOSFET devices.
2. Discussion of the Prior Art
Conventional metal oxide semiconductor (MOS) field effect transistors (FETs) operate with a channel conducting a current having a maximum lateral electrical field just inside the channel junction to the drain. These channel maximum fields accelerate and inject "hot carriers" towards and into the interface of the gate oxide layer over the drain junction, where many hot carriers become trapped as interface states. Interface trapped charge fields oppose the biased gate and drain fields, thereby reducing channel charge mobility, transconductance Gm, drain-to-source current Ids, increasing the switching voltage threshold Vt, and facilitating source-drain breakdown, of the MOSFET. However, in conventional MOSFETs, trapped charge interface state effects are mitigated by the gate overlapping the channel junctions with the source and drain, and overlapping the substrate surface (gate) oxide into which hot carriers are most often injected and trapped. The gate bias counterbalances the field of any trapped charges and partially restores the conductivity of the underlying channel and drain regions.
Conventionally, MOSFET channel maximum lateral electric fields have been reduced through the use of graded or double drain structures such as double diffused drain (DDD) or lightly doped drain (LDD) structures. FIG. 1 illustrates a typical prior art LDD N-channel MOSFET 10 formed from a P-type silicon substrate 12 having an initial upper surface 14 which supports a dielectric layer 16 and 43, 44 which in turn supports a layer of polycrystalline silicon. The polysilicon layer is then etched to leave gate electrode 18 over gate dielectric 16, and a low dosage (around 1E13 atoms/cm.sup.2) of phosphorus is implanted through the exposed LDD surface dielectric 43, 44 into surface 14 to form lightly N-doped LDD regions 20 and 22 in substrate 12. Gate sidewalls 21 and 23 self-align LDD region junctions 24 and 26 to substrate channel 25 with an effective length Leff. Next, two to four thousand angstroms of spacer oxide film is deposited over the structure, and anisotropically etched away to leave gate sidewalls 21 and 23 flanked with oxide spacers 30 and 32 over LDD surface oxide 43 and 44, which shield respectively underlying LDD regions 20 and 22, and to expose surface 14 outside of spacers 30 and 32. Then, the substrate surface 14 is implanted with a heavy dosage (around 5E15 atoms/cm.sup.2) of arsenic, which supplements the phosphorus implant, to form a regularly (N++) doped source region 34 and a regularly (N++) doped drain region 36, which are self-aligned to the outer edges of oxide spacers 30 and 32 and thus offset from channel junctions 24 and 26 by the respective LDD regions 20 and 22 underlying spacers 30 and 32. Lightly doped drain region 22 extends from regular heavily doped drain region 36 to junction 26 with channel 25, and lightly doped source (also "LDD") region 20 extends from the channel's opposite junction 24 to regular heavily doped source region 34. (See "Fabrication of High-Performance LDD-FETs with Oxide Sidewall Spacer Technology" IEEE Trans. Electron Devices, ED-29, pp. 590-596 (1982)).
An N-channel MOSFET 10 is normally operated by applying a positive voltage (approximately 5 V) Vg to the terminal (not shown) of gate 18, a positive voltage (approximately 5 V) Vd to terminal 37 of drain region 36, a zero (ground) voltage Vs to terminal 35 of source region 34, and a zero or negative voltage Vb to terminal 38 of substrate 12. Current Ids flows from drain 36 through channel 25 to source 34.
The LDD device 10 channel maximum lateral electric field, though less than in non-LDD MOSFETs, injects some channel hot carriers along trajectory 40 over LDD junction 26 into the overlying gate oxide 16 and, more than in non-LDD structures, also injects channel hot carriers along trajectory 42 through LDD junction 26 and on upwards into LDD surface oxide 44 on the outside of gate sidewall 23. Over LDD regions, injected hot carriers are more likely to be trapped on, and deplete, the LDD-oxide surface 14 interface than are trapped carriers in non-LDD devices. Charge carriers trapped in LDD oxide 44 are outside the influence of, and not counterbalanced by, the opposing bias on gate 18. In an LDD structure 10, even with only a minor quantity of charge trapped in the LDD surface oxide 44 interface, the LDD region light doping and proportionately weak conductivity is proportionately more offset to a substantially higher resistance. During device 10 operation, ongoing charge trapping gradually increases the LDD region 22 parasitic series resistance, which again degrades the transconductance Gm, switching voltage threshold Vt, and current driveability of device 10.
Referring to FIG. 2, threshold voltage shifts .DELTA.Vt for conventional LDD MOSFETs 10 are typically greater (worse) than for conventional non-LDD MOSFETs when both are stressed at voltages producing equal substrate currents (Isub). (See "Evaluation of LDD MOSFETs based on Hot-Electron-Induced Degradation," IEEE Electron Device Letters, Vol. EDL-5, pp. 162-165 (1984)).
As shown in FIG. 3, over time, the stress-dependent increase in the LDD series resistance reduce the drain current Id (see "Mechanism of Hot Electron Induced Degradation in LDD NMOS-FET" IEDM, pp. 786-789 (1984)).
In addition, the problem of "weak gate-to-source/drain overlap" is encountered in fabrication techniques which implant ions at a tilt or implant ions in low (N-) concentrations of around 1.0E13 atoms/cm.sup.3. Substrate wafer periphery MOSFETs (not shown) are implanted with ions on trajectories angled at approximately seven degrees, and thus gate electrode 18 shadows, and "weakly overlaps," either the source region 34 or drain region 36. A highly biased gate 18 with a weak-or non-overlap over the junction of the source or drain establishes a high electric field which generates hot electrons and causes anomalous "double humps" in substrate current Isub as shown in FIG. 4 (See IEEE Electron Device Letters, Vo. EDL-7 No. 1, pp. 16-19 (1986)).
LDD device 10 conductivity losses have conventionally been accommodated by increasing the concentration of (N-) dopant in LDD regions 20 and 22. In conventional non-LDD arsenic-only MOSFETs, the drain region 36 is heavily N++ doped. Unfortunately, increasing the concentration of dopant in the drain also increases the strength of the electric field beyond junction 26 in substrate 12, increases the junction 26 depletion zone encroachment into channel 25, aggravates the "short channel effect" and the parasitic resistance due to post drive-in diffusion of junctions, and exponentially increases the drain 36-to-substrate 12 current Isubd. When Vd&gt;Vg and device 10 is operating in saturation mode, substrate current Isubd is quite pronounced. Increased substrate current degrades (raises the LDD MOSFET 10 switching voltage threshold Vt, lowers the drain punch-through voltage, and can trigger bipolar "snap-back" latch-up.
Thus, there is a need for an LDD MOSFET structure which reduces and controls interface charge trapping without increasing the substrate currents.